SI4020-I1-FT【PDF 24/32 页】IC TX FSK 915MHZ 5.4V 16-TSSOP

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录57

20页 21页 22页 23页 [24页]25页 26页 27页 28页

Si4020

RESET MODES

The chip will enter into reset mode if any of the following conditions are met:

" Power-on reset: During a power up sequence until the Vdd has reached the correct level and stabilized

" Power glitch reset: Transients present on the V

line

" Software reset: Special control command received by the chip

Power-on reset

After power up the supply voltage starts to rise from 0V. The reset block has an internal ramping voltage reference (reset-ramp

signal), which is rising at 100mV/ms (typical) rate. The chip remains in reset state while the voltage difference between the actual

Vdd and the internal reset-ramp signal is higher than the reset threshold voltage, which is 600 mV (typical). As long as the Vdd voltage

is less than 1.6V (typical) the chip stays in reset mode regardless the voltage difference between the Vdd and the internal ramp

signal.

The reset event can last up to 150ms supposing that the V

reaches 90% its final value within 1ms. During this period the chip does

not accept control commands via the serial control interface.

Power-on reset example:

Power glitch reset

The internal reset block has two basic mode of operation: normal and sensitive reset. The default mode is sensitive, which can be

changed by the appropriate control command (see Related control commands at the end of this section). In normal mode the power

glitch detection circuit is disabled.

There can be spikes or glitches on the V

line if the supply filtering is not satisfactory or the internal resistance of the power supply is

too high. In such cases if the sensitive reset is enabled an (unwanted) reset will be generated if the positive going edge of the V

has

a rising rate greater than 100mV/ms and the voltage difference between the internal ramp signal and the V

reaches the reset

threshold voltage (600 mV). Typical case when the battery is weak and due to its increased internal resistance a sudden decrease of

the current consumption (for example turning off the power amplifier) might lead to an increase in supply voltage. If for some reason

the sensitive reset cannot be disabled step-by-step decrease of the current consumption (by turning off the different stages one by

one) can help to avoid this problem.

Any negative change in the supply voltage will not cause reset event unless the Vdd level reaches the reset threshold voltage (250mV

in normal mode, 1.6V in sensitive reset mode).

If the sensitive mode is disabled and the power supply turned off the Vdd must drop below 250mV in order to trigger a power-on reset

event when the supply voltage is turned back on. If the decoupling capacitors keep their charges for a long time it could happen that

no reset will be generated upon power-up because the power glitch detector circuit is disabled.

Note that the reset event reinitializes the internal registers, so the sensitive mode will be enabled again.

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式